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INTEGRATED CIRCUITS
DATA SHEET
SAA4979H Sample rate converter with embedded high quality dynamic noise reduction and expansion port
Product specification 2002 May 28
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.2 7.2.1 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.4 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.6.8 7.6.9 7.6.10 7.7 7.8 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Digital processing at 1fH level ITU 656 decoder Double window and picture-in-picture processing Black bar detector Dynamic noise reduction Noise estimator Embedded DRAM 3.5-Mbit field memory Digital processing at 2fH level Sample rate conversion Expansion port Panoramic zoom Digital colour transient improvement Y horizontal smart peaking Non-linear phase filter Post processing Triple 10-bit digital-to-analog conversion Microcontroller Host interface I2C-bus interface SNERT-bus I/O ports Watchdog timer Reset System controller Read enable output Read enable input Input enable Horizontal deflection Vertical deflection Auxiliary display signal Read enable 2 Output input enable 2 Reset read 2 Reset write 2 Line-locked clock generation Boundary scan test 8 8.1 8.2 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19
SAA4979H
CONTROL REGISTER DESCRIPTION Host interface detail Special Function Registers (SFRs) LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TRANSFER FUNCTIONS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2002 May 28
2
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
1 FEATURES
SAA4979H
* Digital YUV input according to ITU 656 standard * 4 : 2 : 2 field rate upconversion (50 to 100 Hz or 60 to 120 Hz) * 3.5-Mbit embedded DRAM * Sample rate conversion for linear zoom and compression * Panorama mode * Dynamic noise reduction * Noise estimator * Black bar detection * Luminance horizontal smart peaking * Digital Colour Transient Improvement (DCTI) * Triple 10-bit Digital-to-Analog Converter (DAC) * Line-locked PLL * Expansion port for SAA4992H and SAA4991WP * Double window and Picture-In-Picture (PIP) processing * Embedded 80C51 microcontroller * 32-Kbyte internal ROM (mask programmable) * 512-byte internal RAM 3 QUICK REFERENCE DATA SYMBOL VDDD VDDA VDDO; VDDI VDDP IDDD IDDA Ptot Tamb 4 digital supply voltage analog supply voltage I/O supply voltage protection supply voltage digital supply current analog supply current total power dissipation ambient temperature PARAMETER MIN. 3.0 3.15 3.0 3.0 - - - -20 TYP. 3.3 3.30 3.3 5.0 120 40 - - MAX. 3.6 3.45 3.6 5.5 160 50 0.9 +70 UNIT V V V V mA mA W C * I2C-bus controlled * Synchronous No parity Eight bit Reception and Transmission (SNERT) interface * Boundary Scan Test (BST). 2 GENERAL DESCRIPTION
The SAA4979H provides an economic stand-alone solution for 4 : 2 : 2 field rate upconversion (50 to 100 Hz or 60 to 120 Hz) including the required field memory combined with picture improvement features and dynamic field based noise reduction. The IC contains two digital input channels to allow field or frame based picture-in-picture processing. It also offers a feature expansion port for vector based motion estimation and compensation ICs such as SAA4991WP or SAA4992H.
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME QFP128 DESCRIPTION plastic quad flat package; 128 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height VERSION SOT320-2
SAA4979H
2002 May 28
3
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
5 BLOCK DIAGRAM
SAA4979H
handbook, full pagewidth
LLC1 CLK27 LLC2 SOURCE SELECT DI17 to DI10 DI27 to DI20 8 8 MAIN CHANNEL
NOISE ESTIMATOR
BLACK BAR DETECTOR
SAA4979H
16
Y [7:0] 2 H, V 8 16 FAST SWITCH
ITU 656 DECODER 1 16 SUB CHANNEL 16 ITU 656 DECODER 2 H HREF PLL CLK32
DYNAMIC NOISE REDUCTION
FIELD MEMORY 3.5 MBIT
16
EXT_CLK OSCI OSCO CLK32
SAMPLE RATE CONVERSION 27 to 32 MHz
BYPASS HD, VD, ADS REO, IE, OIE2 RE2, RSTR2 REI, RSTW2 ROM RAM SOURCE SELECT BYPASS UPSAMPLING YI7 to YI0 UVI7 to UVI0 SYSTEM CONTROLLER 2 DOWNSAMPLING H, V YO7 to YO0 UVO7 to UVO0
RST P1.2 to P1.5 SNRST SNDA,SNCL SDA, SCL
MICROCONTROLLER
I/O PORT
SNERTBUS
I2C-BUS
PANORAMIC ZOOM
LUMINANCE CIRCUIT 10 TRIPLE 10-BIT DAC POST PROCESSING NON-LINEAR PHASE FILTER HORIZONTAL SMART Y PEAKING Y BCE TDI BLANKING FRAMING SIDE PANEL CHROMINANCE CIRCUIT 10 10 DCTI UPSAMPLING 4: 2: 2 to 4: 4: 4 UV BOUNDARY SCAN TEST TCK TMS TRST TDO
YOUT
UOUT VOUT
MHC186
Fig.1 Block diagram.
2002 May 28
4
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
6 PINNING SYMBOL VDDO1 RSTR2 RE2 OIE2 VSSO1 RSTW2 DI10 DI11 DI12 DI13 DI14 DI15 DI16 DI17 VSSD1 LLC1 VDDD1 VDDP DI20 DI21 DI22 DI23 DI24 DI25 DI26 DI27 VSSD2 LLC2 VDDD2 TCK TDI TMS TRST n.c. TDO VDDA1 YOUT VSSA1 UOUT VDDA2 2002 May 28 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 to 41 42 43 44 45 46 47 supply digital output (test input) digital output (test input) digital output (test input) ground digital input digital input digital input digital input digital input digital input digital input digital input digital input ground digital input supply supply digital input digital input digital input digital input digital input digital input digital input digital input ground digital input supply digital input digital input digital input digital input - digital output supply analog output ground analog output supply TYPE reset read, source 2 read enable, source 2 output/input enable, source 2 I/O ground 1 reset write, source 2 ITU 656 input bit 0 (LSB), source 1 ITU 656 input bit 1, source 1 ITU 656 input bit 2, source 1 ITU 656 input bit 3, source 1 ITU 656 input bit 4, source 1 ITU 656 input bit 5, source 1 ITU 656 input bit 6, source 1 ITU 656 input bit 7 (MSB), source 1 digital ground 1 27 MHz clock signal, source 1 digital supply voltage 1 (3.3 V) protection supply voltage (5 V) ITU 656 input bit 0 (LSB), source 2 ITU 656 input bit 1, source 2 ITU 656 input bit 2, source 2 ITU 656 input bit 3, source 2 ITU 656 input bit 4, source 2 ITU 656 input bit 5, source 2 ITU 656 input bit 6, source 2 ITU 656 input bit 7 (MSB), source 2 digital ground 2 27 MHz clock signal, source 2 digital supply voltage 2 (3.3 V) test clock test data input test mode select test reset (active LOW) not connected test data output analog supply voltage 1 (3.3 V) Y analog output analog ground 1 -(B - Y) analog output analog supply voltage 2 (3.3 V) 5 DESCRIPTION I/O supply voltage 1 (3.3 V)
SAA4979H
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SYMBOL VOUT VSSA2 AGND BGEXT VDDA3 VSSO2 HD VD VSSA3 VDDI OSCI OSCO CLKEXT VDDD3 CLK32 VSSD3 VDDO2 UVI0 UVI1 UVI2 UVI3 UVI4 UVI5 UVI6 UVI7 YI0 YI1 YI2 YI3 YI4 YI5 YI6 YI7 REI VSSO3 IE REO YO7 YO6 YO5 YO4 2002 May 28 PIN 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 ground ground analog I/O supply ground digital output digital output ground supply analog input analog output digital input supply digital output ground supply digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input ground digital output digital output digital output digital output digital output digital output TYPE analog output analog ground 2 DESCRIPTION -(R - Y) analog output
SAA4979H
analog ground (without substrate contacts) band gap external I/O analog supply voltage 3 (3.3 V) I/O ground 2 horizontal synchronisation output, display part vertical synchronisation output, display part analog ground 3 I/O internal supply voltage (3.3 V) oscillator input oscillator output external clock input digital supply voltage 3 (3.3 V) 32 MHz clock output digital ground 3 I/O supply voltage 2 (3.3 V) UV digital input bit 0 (LSB) UV digital input bit 1 UV digital input bit 2 UV digital input bit 3 UV digital input bit 4 UV digital input bit 5 UV digital input bit 6 UV digital input bit 7 (MSB) Y digital input bit 0 (LSB) Y digital input bit 1 Y digital input bit 2 Y digital input bit 3 Y digital input bit 4 Y digital input bit 5 Y digital input bit 6 Y digital input bit 7 (MSB) read enable input I/O ground 3 input enable read enable output Y digital output bit 7 (MSB) Y digital output bit 6 Y digital output bit 5 Y digital output bit 4 6
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SYMBOL VDDO3 YO3 YO2 YO1 YO0 VSSO4 UVO7 UVO6 UVO5 UVO4 VDDO4 UVO3 UVO2 UVO1 UVO0 VSSD4 VDDD4 ADS SNCL SNDA VSSO5 SNRST SDA SCL P1.5 P1.4 P1.3 P1.2 VDDO5 RST n.c. BCE PIN 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 to 127 128 supply digital output digital output digital output digital output ground digital output digital output digital output digital output supply digital output digital output digital output digital output ground supply digital output digital output digital I/O ground digital I/O digital I/O digital I/O digital I/O digital I/O digital I/O digital I/O supply digital input - digital input TYPE Y digital output bit 3 Y digital output bit 2 Y digital output bit 1 Y digital output bit 0 (LSB) I/O ground 4 UV digital output bit 7 (MSB) UV digital output bit 6 UV digital output bit 5 UV digital output bit 4 I/O supply voltage 4 (3.3 V) UV digital output bit 3 UV digital output bit 2 UV digital output bit 1 UV digital output bit 0 (LSB) digital ground 4 digital supply voltage 4 (3.3 V) auxiliary display signal SNERT clock SNERT serial data microcontroller I/O ground SNERT restart (port 1.0) I2C-bus serial data (port 1.7) I2C-bus clock (port 1.6) port 1 data input/output signal 5 port 1 data input/output signal 4 port 1 data input/output signal 3 port 1 data input/output signal 2 DESCRIPTION I/O supply voltage 3 (3.3 V)
SAA4979H
microcontroller I/O supply voltage (3.3 V) microcontroller reset input not connected boundary scan compliant enable
2002 May 28
7
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
118 RST 117 VDDO5
102 UVO1
101 UVO2
UVO4 98
107 SNCL
116 P1.2
115 P1.3
114 P1.4
128 BCE
113 P1.5
127 n.c.
126 n.c.
125 n.c.
124 n.c.
123 n.c.
122 n.c.
121 n.c.
120 n.c.
111 SDA
112 SCL
119 n.c.
VDDO1 RSTR2 RE2 OIE2 VSSO1 RSTW2 DI10 DI11 DI12 DI13 DI14 DI15 DI16 DI17 VSSD1 LLC1 VDDD1 VDDP DI20 DI21 DI22 DI23 DI24 DI25 DI26 DI27 VSSD2 LLC2 VDDD2 TCK TDI TMS
97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
UVO5
handbook, full pagewidth
100 UVO3 99 VDDO4
110 SNRST 109 VSSO5 108 SNDA
106 ADS 105 VDDD4
104 VSSD4 103 UVO0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
UVO6 UVO7 VSSO4 YO0 YO1 YO2 YO3 VDDO3 YO4 YO5 YO6 YO7 REO IE VSSO3 REI YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4 UVI3 UVI2 UVI1 UVI0
SAA4979H
VSSO2 HD
VD
VSSA3 VDDI
BGEXT VDDA3
OSCO
OSCI
CLKEXT VDDD3
VOUT VSSA2
AGND
CLK32 VSSD3
VDDO2
TDO
VDDA1
UOUT VDDA2
TRST
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
YOUT VSSA1
MHC200
Fig.2 Pin configuration.
2002 May 28
8
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
7 7.1 7.1.1 FUNCTIONAL DESCRIPTION Digital processing at 1fH level ITU 656 DECODER
SAA4979H
The incoming active video data must be limited to 1 to 254, since the data words 00H and FFH are used for identification of the timing reference headers. The digital signal input levels should comply to the CCIR-601 standard (see Fig.3). The data stream is decoded into the internal 4 : 2 : 2 YUV format at a 13.5 MHz clock rate. If required the sign of the UV signals can be inverted for both channels (control inputs: uv_sign1 and uv_sign2). The signal source of the main channel can be selected from both inputs by the internal microcontroller (control input: Select_data_input1).
The SAA4979H provides 2 digital video input channels, which comply to the ITU 656 standard. 720 active video pixels per line are processed at a line-locked clock of 27 MHz, which has to be provided by the signal source. Luminance and chrominance information have to be multiplexed in the following order: CB1, Y1, CR1, Y2, ... Timing reference codes must be inserted at the beginning and end of each video line (see Table 1): * A `Start of Active Video' (SAV) code before the first active video sample (see Table 2) * A `End of Active Video' (EAV) code after the last active video sample (see Table 2). Table 1 ITU data format TIMING REFERENCE CODE (HEX)
BLANKING PERIOD ... 80 10
720 PIXELS YUV 4 : 2 : 2 DATA
TIMING REFERENCE CODE (HEX)
BLANKING PERIOD 10 ...
FF 00 00 SAV CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80
Table 2 BIT 7 1
SAV/EAV format BIT 6 (F) field bit 1st field: F = 0; 2nd field: F = 1 BIT 5 (V) vertical blanking bit VBI: V = 1; active video: V = 0 BIT 4 (H) H = 0 in SAV format; H = 1 in EAV format BIT 3 (P3) BIT 2 (P2) BIT 1 (P1) BIT 0 (P0)
reserved; evaluation not recommended (protection bits according to ITU 656)
2002 May 28
9
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
+ 255 handbook, full pagewidth + 235 white
+ 255 + 240 + 212
blue 100% blue 75%
+ 255 + 240 + 212
red 100% red 75%
+ 128
LUMINANCE 100%
+ 128 U-COMPONENT
colourless
+ 128 V-COMPONENT
colourless
+ 44 + 16 0 black + 16 0
yellow 75% yellow 100%
+ 44 + 16 0
cyan 75% cyan 100%
MHC201
a. Y output range.
b. U output range (CB).
c. V output range (CR).
It should be noted that the input levels are limited to 1 to 254 in accordance with ITU 601/656 standard.
Fig.3 Digital video input levels.
7.1.2
DOUBLE WINDOW AND PICTURE-IN-PICTURE
PROCESSING
7.1.3
BLACK BAR DETECTOR
Data from the sub channel can be inserted into the data stream of the main channel by means of a fast switch. The two channels can be used together with one or two external field memories to implement, for example, double window or PIP processing. Both field based and frame based PIP processing is supported. The synchronization of the sub channel to the main channel is achieved by providing synchronized read signals (RE2 and RSTR2) for the external field memories, whereas the write signals need to be provided together with the incoming data by the external signal source. A multi-PIP mode is also supported by freezing the data in the internal field memory within certain areas via the programmable internal control signal IEint.
Black bar detection searches for the last black line in the upper part of the screen and for the first black line in the lower part of the screen. The detection is done within a programmable window (control inputs: bbd_hstart, bbd_hstop, bbd_vstart and bbd_vstop). To avoid disturbances of LOGOs in the video, the window can be shifted to the horizontal centre of the lines. A video line is considered to be black if the luminance values of that line within the detection window are not greater than a certain slice level (control input: bbd_slice_level) for more than a specific number of pixels (control input: bbd_event_value). The numbers of the first and the last active video line can be read out by the microcontroller (control outputs: bbd_1st_videoline and bbd_last_videoline).
2002 May 28
10
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
7.1.4 DYNAMIC NOISE REDUCTION
SAA4979H
The main function of the noise reduction is shown in Fig.4. It is divided into two signal paths for chrominance and luminance. In principal two operating modes can be used, the fixed and the adaptive mode. In both modes the applied frequency range, in which the noise reduction takes place, can be reduced or not reduced (control input: unfiltered). The noise reduction operates field recursive with an averaging ratio (K factor) between fresh (new) and over previous fields averaged (old) luminance and chrominance values. Noise reduction can be activated by forcing the NREN control bit to HIGH. If NREN is LOW the noise reduction block is bridged via a data multiplexer. In the fixed mode, the noise reduction produces a constant weighted input averaging. Because of smearing effects this mode should not be used for normal operation except for K = 1. The fixed mode can be activated separately for chrominance (control input: chromafix) and luminance (control input: lumafix). In the adaptive mode, the averaging ratio is based on the absolute differences of the inputs of luminance and chrominance respectively. If the absolute difference is low, only a small part of the fresh data will be added. In cases of high difference, much of the fresh data will be taken. This occurs either in situations of movement or where a significant vertical contrast is seen. The relationship between the amount of movement and the K factor values is defined in a look-up table where the steps can be programmed (control input: Kstep).
It should be noted that recursion is done over fields, and that pixel positions between the new and old fields always have a vertical offset of one line. So averaging is not only done in the dimension of time but also in the vertical direction. Therefore averaging vertically on, for example, a vertical black to white edge would produce a grey result. The averaging in chrominance can optionally be slaved to the luminance averaging (control input: Klumatochroma), in that case chrominance differences are not taken into account for the K factor setting of the chrominance signal path. The noise reduction scheme also decreases the cross-colour patterns effectively if the adaptive noise reduction for the averaging in chrominance is slaved to the luminance averaging (control input: Klumatochroma). The cross-colour pattern does not produce an increase of the measured luminance difference, therefore this pattern will be averaged over many fields.
2002 May 28
11
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
handbook, full pagewidth
data input UV7 to UV0 8
Dfielddelay UV7 to UV0 8
data input Y7 to Y0 8
Dfielddelay Y7 to Y0 8
new U/V
old U/V
new Y
old Y
delta U/V
delta Y
LOW-PASS FILTER 1
LOW-PASS FILTER 1
control input: unfiltered LF delta U/V
control input: unfiltered LF delta Y
UV AVERAGE
LOW-PASS FILTER 2 control input: chromafix and Klumatochroma
LOW-PASS FILTER 2
control input: Cadapt_gain
control input: Yadapt_gain
control input: lumafix Klumafix LUT Kluma
LUT
Kchroma Kchromafix Kluma
processed UV control input: noiseshape NOISE SHAPE 8 Dtomemory UV7 to UV0 control input: noiseshape
processed Y NOISE SHAPE 8 Dtomemory Y7 to Y0
MHC202
Fig.4 Schematic diagram of noise reduction.
2002 May 28
12
HF delta Y
ABS/LIMITER
HF delta U/V
ABS/LIMITER
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
7.1.4.1 Band-splitting 7.1.4.4 Noise shape
SAA4979H
The frequencies of the difference signals of luminance (delta Y) and chrominance (delta U/V) can be split optionally into an upper band (HF) and a lower band (LF) with a low-pass filter in both signal paths. The lower frequency band signals (LF delta Y and LF delta U/V) are used as input for the noise reduction function. The lower frequency band of the difference signals can also be used for the motion detection. If, for example, only the lower frequency band contains information, the specific picture content does not move or is moving slowly. Optionally it is possible to bridge the band-splitting (control input: unfiltered = 1).
Possible shadow picture information in the chrominance and luminance path, resulting from a low K factor value, will be eliminated if the noise shaping is activated. The noise shaping function can be switched off via the microcontroller (control input: noiseshape). 7.1.5 NOISE ESTIMATOR
7.1.4.2
Motion detection
The same signals (the noise reduction is applied to) are also used to detect the amount of motion in the difference signals. Therefore, the absolute values of the difference signals are generated and limited to a maximum value. The absolute values of the difference signal of U and V are then averaged. The signals are low-pass filtered for smoothing these signals. The filtered signals are amplified, depending on the setting of the control inputs: Yadapt_gain and Cadapt_gain respectively. The amplified signals, which correlate to the amount of movement in the chrominance or luminance signal path, are transferred into 1 out of 9 possible K factor values via look-up tables. The look-up tables consist of 9 intervals, each related to one K factor. The boundaries between the 9 intervals are defined by 8 programmable steps (control inputs: Kstep0 to Kstep7). The step values are valid for the look-up tables for both the chrominance and the luminance path. For example, signal values between Kstep2 and Kstep3 result in a K factor of K = 3/8.
The noise level of the luminance signal can be measured within a programmable window (control inputs: ne_hstart, ne_hstop, ne_vstart and ne_vstop). The correlation in flat areas is used to estimate the noise in the video signal. A large number of estimates of the noise is calculated for every video field. Such an estimate is obtained by summing absolute differences between current pixel values and delayed pixel values within blocks of 4 pixels. Within the lower part of the total range of possible estimates 15 intervals are defined. Each interval is defined by a lower boundary and an upper boundary. The lower boundary is equal to the number of the interval, whereas the upper boundary has a fixed relationship to the lower boundary (control input: gain_upbnd). The lower boundary is increased or decreased by 1 in each field until an interval is found which contains at least a predefined number of estimates, and is at the same time lowest in the range. The value of the lower boundary of this interval determines the current noise figure output. The predefined number of estimates can be set via the microcontroller (control input: wanted_value), and good results were obtained with a value which is approximately 0.27% of the total number of blocks. For video fields with a lot of noise the number of small differences is very low, that means the number of noise estimates in the lower intervals is close to 0. Contrary to this, for clean sequences this number is very high. This means that for clean sequences the noise estimate figure will be close to 0, and for sequences with a lot of noise the noise estimate figure (control output: nest) will reach 15. To improve the performance of the noise estimator, several functions are implemented which can be controlled by the microcontroller. To increase the sensitivity of the noise measurement a prefilter with different gain settings is available (control input: Ypscale). Since the video content, e.g. sequences with a lot of high frequencies, can influence the noise estimate figure, a detail-counter is built-in.
7.1.4.3
K factor
The amount of noise reduction (field averaging) is described my means of the K factor. When K = 1 no averaging is applied and the new field information is used. When K = 0 no averaging is applied and thus only the old field information is used like in a still picture mode. All values inbetween mean that a weighted averaging is applied. It is possible to use fixed K factor values if the control inputs lumafix or chromafix are set to logic 1. The possible fixed K factor values of the control inputs Klumafix and Kchromafix are given in Table 6.
2002 May 28
13
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
The detail-counter calculates the number of absolute differences between current and previous pixels within a programmable interval defined by the control inputs lb_detail and upb_detail. The result of the 16-bit detail-counter (control outputs: detail_cnt_h and detail_cnt_l) can be used to increase or decrease the result of the noise estimation figure (control input: compensate). In order to reduce the effect of clipping, only the blocks where the sum of the luminance value is within a predefined range are taken into account. The control signal clip_offs can be used to increase or decrease this range. A grey-counter gives information whether enough pixels with values in the grey range are present in a video field (control output: grey_cnt). When this number is lower than a predefined threshold, e.g. for complete fields towards black or white, all blocks are taken into account. 7.2 7.2.1 Embedded DRAM 3.5-MBIT FIELD MEMORY
SAA4979H
In addition, the internal write address pointer is incremented if WEint is HIGH at the positive transition of the SWCKint write clock. The data is latched if WEint was HIGH at the previous positive transition of SWCKint. Input enable (IEint) LOW can also suppress the storage of the data into the memory array but does not influence the write pointer increment. It is used to freeze parts of the field data e.g for PIP processing. The read operation starts with a reset (RSTRint) of the read address pointer during the read enable (REint) LOW phase. The RSTRint LOW-to-HIGH transition, referred to the rising edge of the read clock SRCKint, must be at least 18 clock cycles ahead of the first read data (REint HIGH) and 18 clock cycles after the last read data. The reset read resets the read counter to the lowest address and requests a read operation of the data of the lowest address to the serial read register. Read enable (REint) is used to enable or disable the read operation. The REint controls the data outputs Q0 to Q15. REint HIGH increments the read counter. In parallel to the write operation a read2 operation is done using the same control signals as the write operation: SWCKint, WEint and RSTWint. It reads the old data of the previous field. The data Qold is needed as data input (Dfielddelay) for the noise reduction. When the WEint signal is HIGH it indicates that active video (valid 1fH data) is to be stored. The start of WEint HIGH is triggered by the H and V status bits of the ITU data stream. The start of WEint HIGH can be delayed by the control signals weint_hstart (number of clock delays) and weint_vstart (number of video lines delay). The stop of WEint HIGH is controlled by weint_hstop and weint_vstop. When the IEint signal is HIGH it indicates that active video (valid 1fH data) is also to be stored. The video data is not stored and earlier written data is maintained (frozen) if WEint is HIGH and IEint is LOW. The start of IEint HIGH is triggered by the H and V status bits of the ITU data stream. The start of IEint HIGH can be delayed by the control signals ieint_hstart (number of clock delays) and ieint_vstart (number of video lines delay). The stop of IEint HIGH is controlled by ieint_hstop and ieint_vstop. RSTWint is triggered by the V status bit of the ITU data stream. RSTRint is identical to the VD output signal. REint is provided by the following sample rate conversion to gather 2fH data if it is needed.
The basic functionality of the field memory, which is shown in Fig.5, is similar to the SAA4956TJ. The memory size is extended to 3538944 bits. The data path is 16-bit wide (8-bit chrominance and 8-bit luminance). The field memory is capable of storing, for example, up to 307 video lines of 720 pixels in a 4 : 2 : 2 format. After writing or reading 18 words of 16-bit width, a data transfer is performed from the serial to parallel data registers (writing) or from the parallel to the serial registers (reading). The field memory has one write interface (controller and registers) to store 1fH data and two read interfaces, one to read field delayed 1fH data for the noise reduction function and the other to read 2fH data for the following data processing. Since two asynchronous clock domains are involved (SWCKint as 1fH clock and SRCKint as 2fH clock) the read and write access to the memory array is controlled asynchronously by the memory arbitration logic triggered via request and acknowledge pulses. The write operation starts with a reset write (RSTWint) address pointer operation during the write enable (WEint) LOW phase. The RSTWint LOW-to-HIGH transition, referred to the rising edge of the write clock SWCKint, must be at least 18 clock cycles ahead of the first written data (WEint HIGH) and 18 clock cycles after the last written data. The reset write transfers data temporarily stored in the serial write registers to the memory array and resets the write counter to the lowest address. Write enable (WEint) is used to enable or disable a data write operation. The WEint signal controls the data inputs D0 to D15.
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
handbook, full pagewidth
D15 to D0 and IEint 17
WEint
RSTWint
SWCKint
SERIAL WRITE CONTROLLER write control (requests reset/next)
SERIAL WRITE REGISTER 18-WORD (x 17) 18 x (16 + 1) PARALLEL WRITE REGISTER 18-WORD (x 17) 18 x (16 + 1)
WRITE ADDRESS COUNTER address and control READ2 ADDRESS COUNTER MEMORY ARBITRATION LOGIC READ ADDRESS COUNTER 18 x 16 PARALLEL READ2 REGISTER 18-WORD (x16) 18 x 16 SERIAL READ2 REGISTER 18-WORD (x 16) 18 x 16 PARALLEL READ REGISTER 18-WORD (x 16) 18 x 16 SERIAL READ REGISTER 18-WORD (x 16)
MEMORY ARRAY
221184-WORD (x 16)
read2 acknowledge
read2 control (requests reset/next)
read control (requests reset/next)
read acknowledge
SERIAL READ2 CONTROLLER
SERIAL READ CONTROLLER
16 WEint RSTWint SWCKint Qold15 to Qold0
16 Q15 to Q0 REint RSTRint SRCKint
MHC190
Fig.5 Schematic diagram of 3.5-Mbit field memory.
2002 May 28
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
7.3 7.3.1 Digital processing at 2fH level SAMPLE RATE CONVERSION
SAA4979H
The sample rate conversion block is used to obtain 848 active pixels per line out of the original 720 pixels according to the relation of the two sampling frequencies (32 MHz and 27 MHz). The interpolation for phase positions between the original samples is achieved with a variable phase delay filter with 10 taps for luminance signals and 6 taps for chrominance signals. The conversion to a higher sample frequency of 32 MHz is done to improve the motion estimation performance in combination with external feature ICs, which can process up to 848 pixels per line at a 32 MHz clock. Bypassing this function keeps the original 720 pixels per line (control input: bypass_FSRC). 7.3.2 EXPANSION PORT
An internal bandwidth detector is implemented to detect whether the colour difference signals provide either the full 4 : 2 : 2 bandwidth or a reduced 4 : 1 : 1 bandwidth. Therefore absolute differences between original data and downsampled data are calculated and can be read out by the microcontroller (control output: UV_bw_detect). Low absolute differences indicate that the original data does not contain the full 4 : 2 : 2 bandwidth. This information can be used to switch the upsample and downsample filter on or off (control inputs: bypass_upsampling and bypass_downsampling). Bandwidth detection is done within a programmable window (control inputs: bw_hstart, bw_hstop and bw_vstart, bw_vstop). In the event of a 4 : 1 : 1 format at the input an upconverter to 4 : 2 : 2 is applied with a linear interpolation filter for creation of the extra samples. These are combined with the original samples from the 4 : 1 : 1 stream. The first phase of the YUV data stream is available on the output bus two clock cycles after the rising edge of the REI input signal. The start position, when the first phase of the YUV data stream arrives on the input bus, can be set via the control register exp_hstart. The luminance output signal is in 8-bit straight binary format, whereas the chrominance output signals are in twos complement format. The input data at the expansion slot is expected in the same format. U and V input signals are inverted if the corresponding control bit mid_uv_inv is set.
For a further extension of the system an expansion port is available, which is applicable for either a 4 : 2 : 2 format or a reduced 4 : 1 : 1 format for data input and output at a 32 MHz line-locked clock; see Table 3. However, the internal data is processed in a 8-bit wide 4 : 2 : 2 format. To generate the 4 : 1 : 1 format at the output the U and V samples from the 4 : 2 : 2 data stream are filtered by a low-pass filter, before being subsampled with a factor of 2 and formatted to 4 : 1 : 1 format. Bypassing this function keeps the data in the 4 : 2 : 2 format. Table 3 YUV formats 4 : 1 : 1 FORMAT Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 - - - - Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 - - - - Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 - - - -
OUTPUT PIN YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 UVO7 UVO6 UVO5 UVO4 UVO3 UVO2 UVO1 UVO0
4 : 2 : 2 FORMAT Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 - - - - Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00
INPUT PIN YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4 UVI3 UVI2 UVI1 UVI0
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
7.3.3 PANORAMIC ZOOM
SAA4979H
The panoramic zoom block contains a second sample rate converter, which performs the following tasks: * Linear horizontal sample rate conversion in both zoom and compress direction, with a sample rate conversion factor between 0 and 2, meaning infinite zoom up to a compression with a factor of 2 * Dynamic sample rate conversion e.g. for panorama mode display of 4 : 3 material on a 16 : 9 screen. For linear horizontal zoom or compression the sample rate conversion factor is static during a video line (control input: c0). Positive values of c0 are suitable for compression, negative values result in expansion. In panorama mode the video lines are geometrically expanded towards the sides. The sample rate conversion factor is modulated along the video line. A parabolic shape of the sample rate conversion factor can be obtained with the parameter c2, which controls the second order variation of the sample rate. Negative values of c2 are suitable for panorama mode, positive values result in the inverse mode (amaronap mode). The panoramic zoom block also provides a dynamically controlled delay with an accuracy up to 164 of a pixel and a range of -0.5 to +0.5 lines (control input: hshift). Sufficient accuracy in interpolation for phase positions between the original samples is achieved with a variable phase delay filter with 10 taps for luminance signals and 6 taps for chrominance signals. 7.3.4 DIGITAL COLOUR TRANSIENT IMPROVEMENT
mode, which avoids discolourations in transients within a colour component. 7.3.5
HORIZONTAL SMART
Y PEAKING
A linear peaking is applied, which amplifies the luminance signal in the middle and the upper ranges of the bandwidth. The filtering is an addition of: * The original signal * The original signal high-passed with maximum gain at a frequency of 12fs (sample frequency fs = 32 MHz) * The original signal band-passed with a centre frequency of 14fs * The original signal band-passed with a centre frequency of 4.76 MHz. The band-passed and high-passed signals are weighted with the factors 0, 116, 216, 316, 416, 516, 616 and 816, resulting in a maximum gain difference of 2 dB per step at the centre frequencies. Coring is added to avoid amplification of low amplitudes in the high-pass and band-pass filtered signals, which are considered to be noise. The coring threshold can be programmed as 0 (off), 4, 8, 12 to 60 LSB with respect to the (signed) 10-bit signal. In addition the peaking gain can be reduced depending on the signal amplitude, programming range 0 (no attenuation), 14, 24 and 44. It is also possible to make larger undershoots than overshoots, programming range 0 (no attenuation of undershoots), 14, 24 and 44. A steepness detector is built-in, which provides information for dynamic control of the peaking. For that the maximum absolute value of the band-pass filtered signal within a video field is calculated and can be read out by the microcontroller (control output: steepness_max). 7.3.6 NON-LINEAR PHASE FILTER
The Digital Colour Transient Improvement (DCTI) is intended for U and V signals originating from a 4 : 1 : 1 source. Horizontal transients are detected and enhanced without overshoots by differentiating, make absolute and again differentiating the U and V signals separately. This results in a 4 : 4 : 4 U and V bandwidth. To prevent third-harmonic distortion, which is typical for this processing, a so called over the hill protection prevents peak signals becoming distorted. It is possible to control the following settings via the microcontroller: gain width (see Fig.10), threshold (i.e. immunity against noise), selection of simple or improved first differentiating filter (see Fig.9), limit for pixel shift range (see Fig.11), common or separate processing of U and V signals, hill protection mode (i.e. no discolourations in narrow colour gaps), low-pass filtering for U and V signals (see Fig.12) and a so called super hill
The non-linear phase filter adjusts possible group delay differences in the Y, U and V output channels. The filter coefficients are: [- x (1 - ); 1 + ; - x ] where determines the strength of the filter and determines the asymmetry. The effect of the asymmetry is a decrease in the delay for higher frequencies with 0.5. Control settings are provided for = 0, 18, 28, 38 and = 0, 14, 12.
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
7.3.7 POST PROCESSING
SAA4979H
Blanking is done just before the digital-to-analog conversion by switching Y to a fixed black value and UV to a colourless value. The blanking window is defined by the control inputs: bln_hstart, bln_hstop, bln_vstart and bln_vstop. Side panels are generated by switching the Y, U and V to defined values within a horizontal window (control inputs: sidepanel_hstart and sidepanel_hstop); the 8 MSBs of Y and the 4 MSBs of U and V are programmable (control inputs: sidepanel_y, sidepanel_u and sidepanel_v). Framing e.g. for picture-in-picture mode, can be achieved by another programmable window (control inputs: PIP_frame_hstart, PIP_frame_hstop, PIP_frame_vstart and PIP_frame_vstop). The vertical and horizontal frame width can be programmed from 1 up to 15 pixels (control inputs: PIP_frame_heigth and PIP_frame_width). Framing uses the same colour and luminance values as the side panels.
The range of the Y output signal can be chosen between 9 and 10 bits (control input: output_range). In the event of 9 bits for the nominal signal there is room left for under and overshoot, adding up to a total of 10 bits. In the event of selecting all 10 bits of the luminance digital-to-analog converter for the nominal signal any under or overshoot will be clipped (see Fig.6). The Y samples can be shifted onto 16 positions with respect to the UV samples (control input: y_delay). The zero delay setting is suitable for the nominal case of aligned input data. The other settings provide eight samples with less delay to seven samples with more delay in Y. 7.4 Triple 10-bit digital-to-analog conversion
Three identical 10-bit converters are used to map the 4 : 4 : 4 YUV data to analog levels with a 32 MHz data rate. The polarity of the colour difference signals U and V is switchable by the control bit uv_inv_out. The output ranges are illustrated in Figs 6 and 7 respectively.
(255) handbook, full pagewidth 1023 (235) 940
white
VOY + 1.095 V VOY + 1.0 V
1023
VOY + 1.674 V
(255) 766 (235) 727
white
VOY + 1.0 V
1.0 V (p-p) black
1.0 V (p-p)
(16) 288 (0) 256 (16) 64 (0) 0 black VOY VOY - 0.073 V
VOY
0
VOY - 0.656 V
MHC191
a. Output range = 1.
b. Output range = 0.
Fig.6 Luminance output levels.
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
(255) handbook, full pagewidth 1023 (212) 848 blue 75%
VOU + 1.012 V VOU + 0.665 V
(255) 1023 (212) 848 red 75%
VOV + 0.8 V VOV + 0.575 V
(128) 512
colourless
VOU
(128) 512
colourless
VOV
1.33 V (p-p) yellow 75%
1.05 V (p-p) cyan 75%
(44) 176 (0) 0
VOU - 0.665 V VOU - 1.012 V
(44) 176 (0) 0
VOV - 0.575 V VOV - 0.8 V
MHC192
a. U output level.
b. V output level.
Fig.7 Chrominance output levels.
7.5
Microcontroller
The SAA4979H contains an embedded 80C51 microcontroller core including 512-byte RAM and 32-Kbyte ROM. The microcontroller runs on a 16 MHz clock, generated by dividing the 32 MHz display clock by a factor of 2. 7.5.1 HOST INTERFACE
The I2C-bus slave address of the SAA4979H is 0110100 R/W. During slave transmit mode the SCL LOW period may be extended by pulling SCL to LOW (in accordance with the I2C-bus specification). Detailed information about the software dependent I2C-bus subaddresses of the control registers and a detailed description of the transmission protocol can be found in Application Note "I2C-bus register specification of the SAA4979H". 7.5.3 SNERT-BUS INTERFACE
For controlling internal registers a host interface, consisting of a parallel address and data bus, is built-in. The interface can be addressed as internal AUXRAM via a MOVX type of instruction. The complete range of internal control registers and the corresponding host addresses are described in Section 8.1. User access to these control registers via the I2C-bus can be implemented in the embedded software. 7.5.2 I2C-BUS INTERFACE
The I2C-bus interface in the SAA4979H is used in a slave receive and transmit mode for communication with a central system microcontroller. The standardized bus frequencies of both 100 kHz and 400 kHz can be accommodated.
A SNERT interface is built-in, which operates in a master receive and transmit mode for communication with peripheral circuits such as SAA4991WP or SAA4992H. The SNERT interface replaces the standard UART interface. Contrary to the 80C51 UART interface there are additional special function registers (see Table 10) and there is no byte separation time between address and data.
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
The SNERT interface transforms the parallel data from the microcontroller into 1 or 2 Mbaud SNERT data, switchable via microcontroller. The SNERT-bus consists of three signals: SNCL used as serial clock signal, generated by the SNERT interface; SNDA used as bidirectional data line and SNRST used as reset signal, generated by the microcontroller at port pin P1.0 to indicate the start of a transmission. The read or write operation must be set by the microcontroller. When writing to the bus, 2 bytes are loaded by the microcontroller: one for the address, the other for the data. When reading from the bus, one byte is loaded by the microcontroller for the address, the received byte is the data from the addressed SNERT location. 7.5.4 I/O PORTS
SAA4979H
The system controller is connected to the microcontroller via the host interface. 7.6.1 READ ENABLE OUTPUT
The Read Enable Output (REO) signal is intended for control of an external feature IC. It is a composite signal consisting of a horizontal and a vertical part. The horizontal and vertical positions are programmable (control inputs: reo_hstart, reo_hstop, reo_vstart and reo_vstop). 7.6.2 READ ENABLE INPUT
The Read Enable Input (REI) signal is used in applications with external feature ICs connected to the expansion port. It has to be provided by the external circuit (see Section 7.3.2). 7.6.3 INPUT ENABLE
A parallel 8-bit I/O port (P1) is available, where P1.0 is used as SNERT reset signal (SNRST), P1.2 to P1.5 can be used for application specific control signals, and P1.6 and P1.7 are used as I2C-bus signals (SCL and SDA). 7.5.5 WATCHDOG TIMER
The Input Enable (IE) signal is intended for control of field memories in applications together with an external feature IC connected to the expansion port. It can be directly set or reset via the microcontroller. 7.6.4 HORIZONTAL DEFLECTION
The microcontroller contains an internal Watchdog timer, which can be activated by setting the corresponding special function register PCON.4. Only a synchronous reset will clear this bit. To prevent a system reset the Watchdog timer must be reloaded within a specified time. The Watchdog timer contains an 11-bit prescaler and is therefore incremented every 0.768 ms (16 MHz clock). The time interval between the timers reloading and the occurrence of a reset depends on the reloaded 8-bit value. 7.5.6 RESET
The Horizontal Deflection (HD) signal is for driving a deflection circuit; start and stop values of the horizontal position are programmable in a resolution of 4 clock cycles (control inputs: hd_start and hd_stop). 7.6.5 VERTICAL DEFLECTION
A reset is accomplished by holding the RST pin HIGH for at least 0.75 s while the display clock is running and the supply voltage is stabilized. 7.6 System controller
The Vertical Deflection (VD) signal is for driving a deflection circuit. This signal has a cycle time of 10 ms and the start and stop values of the vertical position are programmable in steps of 16 s (control inputs: vd_start and vd_stop). 7.6.6 AUXILIARY DISPLAY SIGNAL
The system controller provides all necessary internal read and write signals for controlling the embedded field memory. The required control signals (REO and IE) for applications with motion compensation circuits and the drive signals (HD and VD) for the horizontal and vertical deflection power stages are also generated. The system controller also supports double window or picture-in-picture processing in combination with an external field memory by providing the required memory control signals (RE2, RSTW2 and OIE2).
The Auxiliary Display Signal (ADS) is for general purposes; the horizontal and vertical positions are programmable (control inputs: ads_hstart, ads_hstop, ads_vstart and ads_vstop). 7.6.7 READ ENABLE 2
The Read Enable 2 (RE2) signal is intended for control of an external field memory at input channel 2 in picture-in-picture applications. It is a composite signal consisting of a horizontal and a vertical part. The horizontal and vertical positions are programmable (control inputs: re2_hstart, re2_hstop, re2_vstart and re2_vstop).
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Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
7.6.8 OUTPUT/INPUT ENABLE 2 7.7 Line-locked clock generation
SAA4979H
The Output/Input Enable 2 (OIE2) signal is intended for control of one or two external field memories at input channel 2 in picture-in-picture applications. It can be directly set or reset via the microcontroller. 7.6.9 RESET READ 2
An internal PLL generates the 32 MHz line-locked display clock CLK32. The PLL consists of a ring oscillator, DTO and digital control loop. The PLL characteristic is controlled by means of the microcontroller. 7.8 Boundary scan test
The Reset Read 2 (RSTR2) signal is intended for control of the read access of an external field memory at input channel 2 in picture-in-picture applications. It is derived from the internal vertical reference signal of the main channel. 7.6.10 RESET WRITE 2
The SAA4979H has built-in logic and 6 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA4979H follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 6 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI), Boundary-scan Compliant Enable (BCE) and Test Data Output (TDO). To achieve compliance to the "IEEE Std. 1149.1" a logic HIGH has to be applied to the BCE pin. Internal pull-up resistors at the input pins TMS, TRST and TDI are not implemented.
The Reset Write 2 (RSTW2) input is used in picture-in-picture applications with an external field memory at input channel 2, and has to be provided by an external circuit which controls the field memory write access.
8 8.1
CONTROL REGISTER DESCRIPTION Host interface detail Write register at 1fH BIT NAME DESCRIPTION
Table 4
HOST ADDRESS (HEX)
Host address 0102H to 011CH (system control) 0102 0103 0104 0 to 7 weint_vstart 0 to 7 weint_vstop 0 1 2 3 4 5 6 7 0105 0106 0107 0108 weint_vstart (MSB) weint_vstop (MSB) fm1_still pip_2fm_dc sfr sfm re2_vstart (MSB) re2_vstop (MSB) write enable internal memory vertical start (lower 8 of 9 bits) write enable internal memory vertical stop (lower 8 of 9 bits) write enable internal memory vertical start (MSB) write enable internal memory vertical stop (MSB) still picture mode; 0 = normal mode, 1 = still picture mode direct controlled PIP mode; 0 = normal mode, 1 = direct mode field recognition mode; 0 = normal mode, 1 = inverse mode single field mode; 0 = normal mode, 1 = single field mode read enable PIP window vertical start (MSB) read enable PIP window vertical stop (MSB) read enable PIP window vertical start (lower 8 of 9 bits) read enable PIP window vertical stop (lower 8 of 9 bits) read enable PIP window horizontal start (lower 8 of 10 bits) read enable PIP window horizontal stop (lower 8 of 10 bits)
0 to 7 re2_vstart 0 to 7 re2_vstop 0 to 7 re2_hstart 0 to 7 re2_hstop
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
HOST ADDRESS (HEX) 0109
SAA4979H
BIT
NAME
DESCRIPTION
0 to 3 min_dist_maintosub minimum distance between main and sub channel 4 5 6 7 pip_raster_corr pip_on pip_2field mpip_on PIP raster correction; 0 = off, 1 = on PIP mode; 0 = off, 1 = on PIP 2-field mode; 0 = single field mode, 1 = 2-field mode multi-PIP mode; 0 = off, 1 = on vertical position of the display related to acquisition write enable internal memory horizontal start (lower 8 of 10 bits) write enable internal memory horizontal stop (lower 8 of 10 bits)
010A 0112 0113 0114
0 to 7 dispvpos 0 to 7 weint_hstart 0 to 7 weint_hstop
0 to 1 weint_hstart (MSBs) write enable internal memory horizontal start (higher 2 of 10 bits) 2 to 3 weint_hstop (MSBs) write enable internal memory horizontal stop (higher 2 of 10 bits) 4 to 5 re2_hstart (MSBs) 6 to 7 re2_hstop (MSBs) read enable PIP window horizontal start (higher 2 of 10 bits) read enable PIP window horizontal stop (higher 2 of 10 bits) internal H reference horizontal start; 4 pixel resolution internal H reference horizontal stop; 4 pixel resolution input enable internal memory horizontal start (lower 8 of 10 bits) input enable internal memory horizontal stop (lower 8 of 10 bits) input enable internal memory vertical start (lower 8 of 10 bits) input enable internal memory vertical stop (lower 8 of 10 bits) input enable internal memory horizontal start (higher 2 of 10 bits) input enable internal memory horizontal stop (higher 2 of 10 bits) input enable internal memory vertical start (MSB) input enable internal memory vertical stop (MSB) reserved scale of prefilter coefficients: (11, 12, 14, bypass prefilter) compensation value (4-bit signed) reserved gain of upper boundary: 0, 1, 2, 3, 4, 5, 6 and 7 neglect sum over block value if HIGH enable of control bit sob_negl: 0 = disable, 1 = enable clip offset: 1, 2, 4 and 8 reserved wanted value in steps of 1256%, i.e. predefined number of estimates; range: 0 to 255256% lower boundary of detail counter upper boundary of detail counter noise measurement window horizontal start; 4 pixel resolution noise measurement window horizontal stop; 4 pixel resolution noise measurement window vertical start (lower 8 of 9 bits) 22
0116 0117 0118 0119 011A 011B 011C
0 to 7 h656int_hstart 0 to 7 h656int_hstop 0 to 7 ieint_hstart 0 to 7 ieint_hstop 0 to 7 ieint_vstart 0 to 7 ieint_vstop 0 to 1 ieint_hstart (MSBs) 2 to 3 ieint_hstop (MSBs) 4 5 ieint_vstart (MSB) ieint_vstop (MSB)
6 to 7 - 0185 0 to 1 ypscale 2 to 5 compensate 6 to 7 - 0186 0 to 2 gain_upbnd 3 4 7 0187 0188 0189 018A 018B 018C 2002 May 28 sob_negl sel_sob_negl -
Host address 0185H to 018EH (noise estimator)
5 to 6 clip_offs 0 to 7 wanted_value 0 to 7 lb_detail 0 to 7 upb_detail 0 to 7 ne_hstart 0 to 7 ne_hstop 0 to 7 ne_vstart
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
HOST ADDRESS (HEX) 018D 018E
SAA4979H
BIT
NAME
DESCRIPTION noise measurement window vertical stop (lower 8 of 9 bits) noise measurement window vertical start (MSB) noise measurement window vertical stop (MSB) reserved
0 to 7 ne_vstop 0 1 ne_vstart (MSB) ne_vstop (MSB)
2 to 7 - Host address 018FH (front-end control) 018F 0 1 2 Select_data_input1 uv_sign1 uv_sign2
select data input for main channel: 0 = input 2, 1 = input 1 UV sign of main channel 1: 0 = unsigned, 1 = signed UV sign of sub channel 2: 0 = unsigned, 1 = signed reserved step in adaptive curve from K = 116 to K = 18; weight of 1 step in adaptive curve from K = 18 to K = 28; weight of 1 step in adaptive curve from K = 28 to K = 38; weight of 2 step in adaptive curve from K = 38 to K = 48; weight of 2 step in adaptive curve from K = 48 to K = 58; weight of 4 step in adaptive curve from K = 58 to K = 68; weight of 4 step in adaptive curve from K = 68 to K = 78; weight of 8 step in adaptive curve from K = 78 to K = 88; weight of 8 value of the fixed K factor of the luminance; see Table 6 value of the gain of the adaptive curve of the luminance; see Table 5 adaptive (lumafix = 0) or fixed K mode (lumafix = 1) of the luminance value of the fixed K factor of the chrominance; see Table 6 value of the gain of the adaptive curve of the chrominance; see Table 5 adaptive (chromafix = 0) or fixed K mode (chromafix = 1) of chrominance if HIGH: uses luminance K factor for chrominance path if HIGH: band splitting is deactivated, complete difference signals are used if HIGH: noise shaping is activated if HIGH: split screen demo mode is activated noise reduction enable; 0 = off; 1 = on reserved
3 to 7 - 0190 0191 0192 0193 0194 0 to 3 Kstep0 4 to 7 Kstep1 0 to 3 Kstep2 4 to 7 Kstep3 0 to 3 Kstep4 4 to 7 Kstep5 0 to 3 Kstep6 4 to 7 Kstep7 0 to 3 Klumafix 4 to 6 Yadapt_gain 7 0195 lumafix 0 to 3 Kchromafix 4 to 6 Cadapt_gain 7 0196 0 1 2 3 4 chromafix Klumatochr unfiltered noiseshape splitscreen NREN
Host address 0190H to 0196H (noise reduction)
5 to 7 - 019A 019B 0 to 5 bbd_event_value 6 to 7 - 0 to 5 bbd_slice_level 6 7 019C bbd_vstop (MSB) bbd_vstart (MSB)
Host address 019AH to 019FH (black bar detection) black bar detection event value reserved black bar detection slice level black bar detection window vertical stop (MSB) black bar detection window vertical start (MSB) black bar detection window horizontal start; 4 pixel resolution
0 to 7 bbd_hstart
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
HOST ADDRESS (HEX) 019D 019E 019F Table 5
SAA4979H
BIT
NAME
DESCRIPTION black bar detection window horizontal stop; 4 pixel resolution black bar detection window vertical start (lower 8 of 9 bits) black bar detection window vertical stop (lower 8 of 9 bits)
0 to 7 bbd_hstop 0 to 7 bbd_vstart 0 to 7 bbd_vstop
Gain settings of adaptive values for chrominance and luminance Yadapt_gain/Cadapt_gain [2:0] GAIN HEX 00 01 02 03 04 05 06 07 DECIMAL 0 1 2 3 4 5 6 7
1 8 2 8 4 8 8 8 16 8 32 8 64 8 128 8
Table 6
Settings of fixed K factor values Klumafix/Kchromafix [3:0] K factor HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DECIMAL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
1 2 3 4 5 6 7 8 9 16 16 16 16 16 16 16 16
16 10 16 11 16 12 16 13 16 14 16 16 16
2002 May 28
24
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
Table 7 Write register at 2fH BIT NAME DESCRIPTION
SAA4979H
HOST ADDRESS (HEX)
Host address 0222H to 023FH (system control) 0222 0223 0224 0225 0226 0227 0 to 7 0 to 7 0 to 7 0 to 7 0 to 3 4 to 7 0 to 1 2 to 3 4 to 7 0228 0 to 2 3 to 4 6 to 7 0229 022A 022B 0 to 7 0 to 7 0 1 2 3 4 5 6 7 022C 022D 022E 0 to 7 0 to 7 0 to 1 2 to 3 4 to 5 6 to 7 0230 0231 0234 0235 0238 0 to 7 0 to 7 0 to 7 0 to 7 0 to 1 2 to 3 4 to 7 023A 2002 May 28 0 to 7 vd_vstart vd_vstop reo_vstart reo_vstop dspflds - reo_vstart (MSBs) reo_vstop (MSBs) - vd_vstart (MSBs) vd_vstop (MSBs) - ads_hstart ads_hstop vres_dis crn_direct dr_aabb - gen_mode ie_fm2 smooth_lock - ads_vstart ads_vstop ads_hstart (MSBs) ads_hstop (MSBs) ads_vstart (MSBs) ads_vstop (MSBs) hd_hstart hd_hstop reo_hstart reo_hstop reo_hstart (MSBs) reo_hstop (MSBs) - fl vertical deflection pulse start (lower 8 of 11 bits) vertical deflection pulse stop (lower 8 of 11 bits) read enable output window vertical start (lower 8 of 10 bits) read enable output window vertical stop (lower 8 of 10 bits) number of display fields minus 1 reserved read enable output window vertical start (higher 2 of 10 bits) read enable output window vertical stop (higher 2 of 10 bits) reserved vertical deflection pulse start (higher 3 of 11 bits) vertical deflection pulse start (higher 3 of 11 bits) reserved auxiliary display signal horizontal start (lower 8 of 10 bits) auxiliary display signal horizontal stop (lower 8 of 10 bits) internal vertical reset; 0 = enable; 1 = disable direct vertical frame synchronization; 0 = disable; 1 = enable display raster mode; 0 = standard VD synchronization; 1 = AABB synchronization; VD delayed for the first 50 Hz field reserved generator mode; 0 = off; 1 = on input enable signal (output IE) smooth lock synchronization mode; 0 = off; 1 = on reserved auxiliary display signal vertical start (lower 8 of 10 bits) auxiliary display signal vertical stop (lower 8 of 10 bits) auxiliary display signal horizontal start (higher 2 of 10 bits) auxiliary display signal horizontal stop (higher 2 of 10 bits) auxiliary display signal vertical start (higher 2 of 10 bits) auxiliary display signal vertical stop (higher 2 of 10 bits) horizontal deflection pulse start; 4 pixels resolution horizontal deflection pulse stop; 4 pixels resolution read enable output window horizontal start (lower 8 of 10 bits) read enable output window horizontal stop (lower 8 of 10 bits) read enable output window horizontal start (higher 2 of 10 bits) read enable output window horizontal stop (higher 2 of 10 bits) reserved display field length (lower 8 of 11 bits) 25
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
HOST ADDRESS (HEX) 023B 023C 023D 023E 023F
SAA4979H
BIT 0 to 2 3 to 7 0 to 7 0 to 7 0 to 7 0 to 1 2 to 3 4 to 7 fl (MSBs) - hp1
NAME
DESCRIPTION display field length (higher 3 of 11 bits) reserved frame synchronization pulse position; 4 pixels resolution display locking window vertical start (lower 8 of 10 bits) display locking window vertical stop (lower 8 of 10 bits) display locking window vertical start (higher 2 of 10 bits) display locking window vertical stop (higher 2 of 10 bits) reserved
dsplock_vstart dsplock_vstop dsplock_vstart (MSBs) dsplock_vstop (MSBs) - c2 c0 hshift (LSBs) hshift (MSBs) nrln nrpx_div4 transparent_mode c0 (MSB) nrln (MSBs) - mid_hstart bw_hstop bw_hstart bw_hstop bw_hstart (MSBs) bw_hstop (MSBs) bw_hstart (MSBs) bw_hstop (MSBs) bypass_downsampling mid_uv_inv bypass_FSRC - be_hstart be_hstop be_hstart be_hstop
Host address 0287H to 028DH (panoramic zoom) 0287 0288 0289 028A 028B 028C 028D 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 0 1 2 to 3 4 to 7 compression or expansion non-linearity value linear compression or expansion value (lower 8 of 9 bits) horizontal pixel shift (lower 8 of 16 bits) horizontal pixel shift (higher 8 of 16 bits) number of lines per field (lower 8 of 10 bits) number of pixels per line divided-by-4 bypass panoramic zoom: 0 = panoramic zoom active, 1 = bypass linear compression or expansion value (MSB) number of lines per field (higher 2 of 10 bits) reserved
Host address 0280H to 0284H and 0290H (mid-end control) 0280 0281 0282 0283 0284 0 to 7 0 to 7 0 to 7 0 to 7 0 to 1 2 to 3 4 to 5 6 to 7 0290 0 1 2 3 to 7 bandwidth detection window horizontal start (lower 8 of 10 bits) bandwidth detection window horizontal stop (lower 8 of 10 bits) bandwidth detection window vertical start (lower 8 of 10 bits) bandwidth detection window vertical stop (lower 8 of 10 bits) bandwidth detection window horizontal start (higher 2 of 10 bits) bandwidth detection window horizontal stop (higher 2 of 10 bits) bandwidth detection window vertical start (higher 2 of 10 bits) bandwidth detection window vertical stop (higher 2 of 10 bits) bypass downsampling: 0 = downsampling active, 1 = bypass inverts UVO output signals: 0 = no inversion, 1 = inversion bypass Fixed Sample Rate Converter (FSRC): 0 = FSRC active, 1 = bypass reserved
Host address 0298H to 029FH (back-end control) 0298 0299 029A 029B 0 to 7 0 to 7 0 to 7 0 to 7 back-end window horizontal start (lower 8 of 10 bits) back-end window horizontal stop (lower 8 of 10 bits) back-end window vertical start (lower 8 of 10 bits) back-end window vertical stop (lower 8 of 10 bits)
2002 May 28
26
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
HOST ADDRESS (HEX) 029C
SAA4979H
BIT 0 to 1 2 to 3 4 to 5 6 to 7
NAME be_hstart (MSBs) be_hstop (MSBs) be_hstart (MSBs) be_hstop (MSBs) exp_hstart exp_hstart (MSBs) - bypass_upsampling extern_device - steepness_vstart steepness_vstop steepness_hstart steepness_hstop pk_alpha pk_beta pk_tau
DESCRIPTION back-end window horizontal start (higher 2 of 10 bits) back-end window horizontal stop (higher 2 of 10 bits) back-end window vertical start (higher 2 of 10 bits) back-end window vertical stop (higher 2 of 10 bits) expansion port input window: horizontal start (lower 8 of 10 bits) expansion port input window: horizontal start (higher 2 of 10 bits) reserved bypass upsampling: 0 = upsampling active, 1 = bypass external device multiplexer: 0 = internal, 1 = data from external device reserved
029D 029E 029F
0 to 7 0 to 1 2 to 7 0 1 2 to 7
Host address 02A0H to 02A6H (dynamic horizontal smart peaking) 02A0 02A1 02A2 02A3 02A4 0 to 7 0 to 7 0 to 7 0 to 7 0 to 2 3 to 5 02A5 0 to 2 steepness detection window vertical start; 4 lines resolution steepness detection window vertical stop; 4 lines resolution steepness detection window horizontal start; 4 pixels resolution steepness detection window horizontal stop; 4 pixels resolution peaking : 116 (0, 1, 2, 3, 4, 5, 6, 8) peaking : 116 (0, 1, 2, 3, 4, 5, 6, 8) reserved peaking : 116 (0, 1, 2, 3, 4, 5, 6, 8) peaking amplitude dependent attenuation: 14 (0, 1, 2, 4) peaking attenuation of undershoots: 14 (0, 1, 2, 4) reserved peaking coring threshold: 0, 4, 8 , 12 , 16 to 60 LSB output range: output range = 0: 9 bits for the nominal output signal, black level: 288 and white level: 727; output range = 1: 10 bits for the nominal output signal, black level: 64 and white level: 940 reserved
6 and 7 - 3 and 4 pk_delta 5 and 6 pk_neggain 7 02A6 0 to 3 4 - pk_corthr output_range
5 to 7
- dcti_gain dcti_threshold dcti_ddx_sel dcti_separate dcti_protection dcti_filteron dcti_superhill
Host address 02A8H and 02A9H (DCTI) 02A8 0 to 2 3 to 6 7 02A9 2 3 4 5 DCTI gain: 0, 1, 2, 3, 4, 5, 6 and 7 DCTI threshold: 0, 1 to 15 DCTI selection of first differentiating filter; see Fig.9 DCTI limit for pixel shift range: 0, 1, 2 and 3 DCTI separate processing of U and V signals; 0 = off; 1 = on DCTI over the hill protection; 0 = off; 1 = on DCTI post-filter; 0 = off; 1 = on DCTI super hill mode; 0 = off; 1 = on reserved
0 and 1 dcti_limit
6 and 7 -
2002 May 28
27
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
HOST ADDRESS (HEX)
SAA4979H
BIT
NAME
DESCRIPTION
Host address 02B0H to 02BBH and 02AAH (post processing) 02B0 02B1 02B2 02B3 02B4 0 to 3 4 to 7 0 to 7 0 to 7 0 to 7 0 to 3 4 5 6 to 7 02B5 02B6 02B7 02B8 02B9 0 to 7 0 to 7 0 to 7 0 to 7 0 to 1 2 to 3 4 to 5 6 to 7 02BA 0 to 1 2 to 3 4 to 5 6 to 7 02BB 02BC 02BD 02BE 02BF 0 to 7 0 to 7 0 to 7 0 to 7 0 to 1 2 to 3 4 to 5 6 to 7 02AA 0 to 3 4 to 7 sidepanel_u sidepanel_v sidepanel_y sidepanel_hstart sidepanel_hstop y_delay uv_inv_out y_dac_current - bln_hstart bln_hstop bln_vstart bln_vstop bln_hstart (MSBs) bln_hstop (MSBs) bln_vstart (MSBs) bln_vstop (MSBs) nlp_u nlp_l sidepanel_hstart (LSBs) sidepanel_hstop (LSBs) PIP_frame_hstart PIP_frame_hstop PIP_frame_vstart PIP_frame_vstop PIP_frame_vstart (MSBs) PIP_frame_vstop (MSBs) PIP_frame_hstop (MSBs) PIP_frame_width (MSBs) side panel colour U value (4 MSB) side panel colour V value (4 MSB) side panel luminance value (8 MSB) side panel start position (higher 8 of 10 bits) side panel stop position (higher 8 of 10 bits) Y delay relative to UV channel, in clock cycles: -8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, and 7 inverts UV output signals: 0 = no inversion, 1 = inversion gain Y digital-to-analog converter: 0 = 2 A/bit (range 1), 1 = 4 A/bit (range 0); see Fig.6 reserved blanking window horizontal start position (lower 8 of 10 bits) blanking window horizontal stop position (lower 8 of 10 bits) blanking window vertical start position (lower 8 of 10 bits) blanking window vertical stop position (lower 8 of 10 bits) blanking window horizontal start position (higher 2 of 10 bits) blanking window horizontal stop position (higher 2 of 10 bits) blanking window vertical start position (higher 2 of 10 bits) blanking window vertical stop position (higher 2 of 10 bits) non-linear phase filter settings : (0, 14, 12, 12) non-linear phase filter settings : (0, 18, 28, 38) side panel start position (lower 2 of 10 bits) side panel stop position (lower 2 of 10 bits) PIP frame: horizontal start position (lower 8 of 10 bits) PIP frame: horizontal stop position (lower 8 of 10 bits) PIP frame: vertical start position (lower 8 of 10 bits) PIP frame: vertical stop position (lower 8 of 10 bits) PIP frame: vertical start position (higher 2 of 10 bits) PIP frame: vertical stop position (higher 2 of 10 bits) PIP frame: horizontal stop position (higher 2 of 10 bits) PIP horizontal frame width (0 to 15 pixel)
PIP_frame_hstart (MSBs) PIP frame: horizontal start position (higher 2 of 10 bits)
PIP_frame_height (MSBs) PIP vertical frame width (0 to 15 pixel)
2002 May 28
28
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
HOST ADDRESS (HEX)
SAA4979H
BIT
NAME
DESCRIPTION
Host address 0300H to 0305H (PLL) 0300 0301 0 to 2 3 to 7 0 to 1 2 to 4 5 6 7 0302 0303 0304 0 to 7 0 to 7 0 1 2 to 7 0305 0 to 2 3 to 7 Table 8 PLL_cd_value PLL_ck_value - PLL_idto (MSBs) 0 PLL_off_hif PLL_open PLL_idto2 PLL_idto1 PLL_freq_shift PLL_limiter_off - PLL_cd_adapt PLL_ck_adapt damping factor time constant reserved signed increment offset of DTO (MSBs) to be cleared freeze frequency disable outer loop: 0 = outer loop closed, 1 = outer loop open signed increment offset of DTO (higher byte) signed increment offset of DTO (lower byte) operating frequency shift: 0 = no shift, 1 = frequency shift of 8% PLL frequency limiter of outer loop: 0 = limiter on, 1 = limiter off reserved damping factor in adaptive mode time constant in adaptive mode
Read register at 1fH BIT NAME DESCRIPTION
HOST ADDRESS (HEX)
Host address 0142H and 0143H (system control) 0142 0143 0 to 7 0 to 1 2 3 to 7 fieldinf filedinf (MSBs) frg - nest - nest_filt detail_cnt_h detail_cnt_l grey_cnt result of field length measurement (lower 8 of 10 bits) result of field length measurement (higher 2 of 10 bits) field recognition of incoming source reserved
Host address 01C0H to 01C4H (noise estimator) 01C0 01C1 01C2 01C3 01C4 0 to 3 4 to 7 0 to 7 0 to 7 0 to 7 0 to 7 noise estimation result reserved noise estimation value filtered output of detail counter, higher byte output of detail counter, lower byte output of grey counter
Host address 01CAH and 01CBH (black bar detection) 01CA 01CB 0 to 6 7 0 to 7 bbd_1st_videoline bbd_last_videoline (MSB) bbd_last_videoline line number of first video line line number of last video line (MSB) line number of last video line
2002 May 28
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
Table 9 Read register at 2fH BIT NAME DESCRIPTION
SAA4979H
HOST ADDRESS (HEX)
Host address 0242H (system control) 0242 0 to 3 4 5 to 7 dspflds dsp_unlock - UV_bw_detect number of display fields - 1 display unlock: 0 = normal operation, 1 = vertical display timing unlocked reserved
Host address 02C8H (UV bandwidth detection) 02C8 0 to 7 result of UV bandwidth detection (unsigned value)
Host address 02D0H (dynamic peaking) 02D0 8.2 0 to 7 steepness_max result of steepness detection (unsigned value)
Special Function Registers (SFRs)
Table 10 SNERT-bus control SFR ADDRESS (HEX) BIT READ/WRITE NAME DESCRIPTION
Special function register 9AH (SNCON); reset value: 00H 9A 0 1 read read and write TRM REC SNERT transmit busy flag: TRM is set to logic 1 after SFR 9CH (SNWDA) is accessed, after a transmission TRM is set to logic 0 SNERT receive busy flag: if REC is set to logic 1 the contents of SFR 9BH (SNADD) is transmitted, after reception is completed REC is set to logic 0 reserved SNERT baud rate: 0 = 1 MHz, 1 = 2 MHz
2 to 6 7
- read and write
- MB2
Special function register 9BH (SNADD) 9B 0 to 7 write SNADD SNERT address
Special function register 9CH (SNWDA) 9C 0 to 7 write SNWDA SNERT data to be transmitted
Special function register 9DH (SNRDA) 9D 0 to 7 read SNRDA data received from SNERT-bus
2002 May 28
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
Table 11 Power control SFR ADDRESS (HEX) BIT READ/WRITE NAME DESCRIPTION
SAA4979H
Special function register 87H (PCON); reset value: 00H 87 0 1 2 to 3 4 read and write read and write - read and write IDL PD - WLE EW 5 6 7 read and write read and write - RFI ARD - Idle mode bit: 0 = normal operation, 1 = Idle mode operation Power-down bit: 0 = normal operation, 1 = Power-down mode reserved Watchdog load enable: 0 = loading of Watchdog timer disabled, 1 = loading of Watchdog timer enabled enable Watchdog: 0 = Watchdog disabled, 1 = Watchdog enabled; once this bit is set only a synchronous reset can clear it radio frequency interference bit: disables toggling of internal ALE signal during on-chip program access if set to logic 1 auxiliary RAM disable: setting this bit will force MOVX instructions to access off-chip memory instead of AUXRAM reserved
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDD VDDA VDDI VDDO VDDP VI VI IDD(tot) IO Ptot Tstg Tj Tamb Ves PARAMETER digital supply voltage analog supply voltage internal I/O supply voltage I/O supply voltage supply voltage for protection circuits input voltage for all digital input pins input voltage for all digital I/O pins total supply current short circuit output current total power dissipation storage temperature junction temperature ambient temperature electrostatic handling voltage note 1 note 2 Notes 1. Machine model class B, equivalent to discharging a 200 pF capacitor through a 0 series resistor (0 is actually 0.75 H + 10 ). 2. Human body model class B, equivalent to discharging a 100 pF capacitor through a 1500 series resistor. VDDP = 5 V VDDP = 3.3 V VDDD = 3.3 V CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 - - - -25 0 0 -200 -2000 MAX. +4.0 +4.0 +4.0 +3.8 +5.5 +5.5 +3.8 +3.8 300 30 1.2 +150 +125 +70 +200 +2000 UNIT V V V V V V V V mA mA W C C C V V
2002 May 28
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air
SAA4979H
VALUE 45
UNIT K/W
11 CHARACTERISTICS VDDD = 3.0 to 3.6 V; VDDO = 3.0 to 3.6 V; VDDA = 3.15 to 3.45 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supplies VDDD VDDA VDDI VDDO VDDP IDDD IDDA IDDI IDDO IDDP INL DNL digital supply voltage analog supply voltage internal I/O supply voltage I/O supply voltage protection supply voltage digital supply current analog supply current internal I/O supply current I/O supply current protection supply current 3.0 3.15 3.0 3.0 3.0 - - - - - -2 -1 output range = 0: nominal amplitude digital 288 to 727; output range = 1: nominal amplitude digital 64 to 940 output range = 0 output range = 1 0.94 3.3 3.30 3.3 3.3 5.0 120 40 0 10 0 - - 1.00 3.6 3.45 3.6 3.6 5.5 160 50 2 40 1 V V V V V mA mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Output transfer function (sample rate 32 MHz/10 bits) integral non linearity differential non linearity +2 +1 LSB LSB
Luminance output signal: pin YOUT Vo(p-p) Y output level (peak-to-peak value) 1.06 V
Vo(black) Ro CL S/N
Y black level (voltage at 288) Y black level (voltage at 64) output resistance capacitive load signal-to-noise ratio
0.837 0.836 - -
0.891 0.889 75 - -
0.944 0.942 85 25 -
V V pF dB
nominal amplitude; 0 to 10 MHz
46
Colour difference output signals: pins UOUT and VOUT Vo(p-p) U output level (peak-to-peak value) V output level (peak-to-peak value) for saturated colour bar with 75% of maximum amplitude for saturated colour bar with 75% of maximum amplitude 1.25 1.33 1.41 V
0.99
1.05
1.11
V
2002 May 28
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SYMBOL Vo(colourless) GD(U-V) Ro CL S/N PARAMETER U colourless level (voltage at 512) V colourless level (voltage at 512) gain matching U to V output resistance capacitive load signal-to-noise ratio nominal amplitude; 0 to 10 MHz IOH = -0.5 mA IOL = 0.5 mA IOH = -2.0 mA IOL = 2.0 mA CONDITIONS MIN. 1.32 1.32 - - - 46 TYP. 1.40 1.40 1 75 - -
SAA4979H
MAX. 1.48 1.48 3 85 25 -
UNIT V V % pF dB
Digital output signals: pins OIE2, RSTR2 and RE2 VOH VOL VOH VOL VIH VIL ILI VIH VIL IIH IIL VIH VIL ILI VOH VOL VIH VIL IIH IIL VOH VOL VIH VIL ILI HIGH-level output voltage LOW-level output voltage 2.4 - 2.4 - 2 - - 2.0 - - - 2.0 - - IOH = -2.0 mA IOL = 2.0 mA 2.4 0 2.0 0 - - IOH = -2.0 mA IOL = 2.0 mA 2.4 0 2.0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - 0.4 - 0.4 V V
Digital output signals: all pins except OIE2, RSTR2 and RE2 HIGH-level output voltage LOW-level output voltage V V
Digital input signals: pins DI1, DI2, LLC1, LLC2, RSTW2, TDI, TMS,TCK, BCE and TRST HIGH-level input voltage LOW-level input voltage input leakage current VDDP + 0.3 V 0.8 10 V A V V A A V V A V V V V A A V V V V A
Digital input signals: pins UVI, YI, REI and RST HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current 5.5 0.8 100 10
Digital input signal: pin CLKEXT HIGH-level input voltage LOW-level input voltage input leakage current 5.5 0.8 10 - 0.4 3.8 0.8 10 100 - 0.4 5.5 0.8 10
Digital input/output signals: pins SNRST and P1.2 to P1.5 HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current
Digital input/output signal: pin SNDA HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage input leakage current
2002 May 28
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SYMBOL PARAMETER CONDITIONS - 4 - 3 MIN. - - - - - - - - 37 50 - - 31.25 50 - - TYP.
SAA4979H
MAX.
UNIT
Data output timing: pins OIE2, RSTR2 and RE2 (CL = 15 pF); timing referenced to LLC1 td(o) th(o) output delay time output hold time see Fig.8 see Fig.8 26 - ns ns
Data output timing: pins YO, UVO, IE, REO, ADS, HD and VD (CL = 15 pF); timing referenced to CLK32 td(o) th(o) tsu(i) th(i) tsu(i) th(i) Tcy clk tr tf Tcy clk tr tf output delay time output hold time see Fig.8 see Fig.8 20 - - - - - 40 60 5 5 ns ns
Data input timing: pins RSTW2, DI1 and DI2; timing referenced to LLC1 input set-up time input hold time see Fig.8 see Fig.8 4 3 ns ns
Data input timing: pins YI, UVI and REI; timing referenced to CLK32 input set-up time input hold time see Fig.8 see Fig.8 4 3 ns ns
Clock input timing: pins LLC1 and LLC2 cycle time clock duty factor clock rise time clock fall time see Fig.8 see Fig.8 34 40 - - 29.00 40 see Fig.8 see Fig.8 - - ns % ns ns
Clock input timing: pin CLKEXT cycle time clock duty factor clock rise time clock fall time 34.00 60 5 5 ns % ns ns
Clock output timing: pin CLK32 (CL = 25 pF) Tcy clk tr tf line-line cycle time clock duty factor output rise time output fall time see Fig.8 see Fig.8 26.00 45 - - - 31.25 50 - - 0.4 - - - - - - - 38.00 55 4 4 ns % ns ns
PLL function (base frequency 32 MHz) sigma value of line-to-line jitter locked to stable H signal 1.0 ns
I2C-bus signals: pins SDA and SCL; note 1 VIH VIL Vhys VOL ILI fSCL tr tf HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current SCL clock frequency rise time of SDA and SCL fall time of SDA and SCL IOL = 3.0 mA 0.7VDDO - - - - - - 5.5 0.3VDDO - 0.4 10 400 0.3 0.3 V V V V A kHz s s
0.05VDDO -
2002 May 28
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SYMBOL tHD;STA tHD;DAT tLOW tHIGH tSU;DAT tSU;STA tSU;STO tBUF PARAMETER hold time START condition data hold time SCL LOW time SCL HIGH time data set-up time set-up time repeated START set-up time STOP condition bus free time between a STOP and START condition CONDITIONS 0 1.3 0.6 100 0.6 0.6 1.3 MIN. 0.6 - - - - - - - - TYP.
SAA4979H
MAX. - 0.9 - - - - - -
UNIT s s s s ns s s s
SNERT-bus timing (valid for both 1 and 2 Mbaud): pins SNDA and SNCL; note 2 tsu(i) th(i) th(o) tsu(o) tcy(SNCL) tSNRSTH Notes 1. The AC characteristics are in accordance with the I2C-bus specification for fast mode (clock frequency maximum 400 kHz). Information about the I2C-bus can be found in the brochure "I2C-bus and how to use it" (order number 9398 393 40011). 2. More information about the SNERT-bus protocol can be found in Application Note "The SNERT-bus specification" (AN95127). input set-up time input hold time output hold time output set-up time SNCL cycle time SNRST pulse HIGH time 80 0 50 260 500 500 200 - - - - - - - - - - - 1000 - - ns ns ns ns ns ns ns
td(SNRST-DAT) delay SNRST pulse to data
handbook, full pagewidth
tr
tf 2.4 V
CLOCK
1.5 V 0.6 V t h(i) t su(i) 2.0 V
INPUT DATA 0.8 V t d(o) t h(o) 2.4 V OUTPUT DATA 0.4 V
MHC203
Fig.8 Timing diagram.
2002 May 28
35
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
12 TRANSFER FUNCTIONS
SAA4979H
MHC204
handbook, halfpage
1
signal amplitude 0.8
(1)
(2)
0.6
0.4
0.2
0 0 0.05 0.1 0.15 0.2 f/fs 0.25
(1) dcti_ddx_sel = 1. (2) dcti_ddx_sel = 0.
Fig.9 DCTI first differentiating filter; transfer function with variation of control signal dcti_ddx_sel.
handbook, full pagewidth
MHC205
500 digital signal 400 amplitude 300
(4) (3) (1) (2)
200 100 0
(5)
samples -100 -200 -300 (1) (2) (3) (4) (5) input signal. gain = 1. gain = 3. gain = 5. gain = 7. -400 -500
Fig.10 DCTI with variation of gain setting (limit = 1).
2002 May 28
36
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
handbook, full pagewidth
500 digital signal 400 amplitude 300 200 100 0
(4) (3) (2) (1)
MHC206
samples -100 -200 -300 -400 (1) (2) (3) (4) input signal. limit = 1. limit = 2. limit = 3. -500
Fig.11 DCTI with variation of limit setting (gain = 7).
handbook, halfpage
1.2
MHC207
signal amplitude 0.8
0.4
0 0 0.1 0.2 0.3 0.4 f/fs 0.5
Fig.12 DCTI post-filter transfer function.
2002 May 28
37
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
handbook, full pagewidth
10
MHC208
signal amplitude (dB) 8
(7)
(6) (5)
6
(4)
(3)
4
(2)
2
(1)
0 0 = 116. = 216. = 316. = 416. = 516. = 616. = 816. 0.1 0.2 0.3 0.4 f/fs 0.5
(1) (2) (3) (4) (5) (6) (7)
Fig.13 Transfer function of the peaking high-pass filter with variation of ( = 0; = 0).
2002 May 28
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
handbook, full pagewidth
10
MHC209
signal amplitude (dB) 8
(7)
(6) (5)
6
(4)
(3)
4
(2)
2
(1)
0 0 (1) (2) (3) (4) (5) (6) (7) = 116. = 216. = 316. = 416. = 516. = 616. = 816. 0.1 0.2 0.3 0.4 f/fs 0.5
Fig.14 Transfer function of the peaking band-pass with variation of ( = 0; = 0).
2002 May 28
39
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
handbook, full pagewidth
10
MHC210
signal amplitude (dB) 8
(7)
(6)
6
(5) (4)
4
(3)
(2)
2
(1)
0 0 (1) = 116. (2) = 216. (3) = 316. (4) = 416. (5) = 516. (6) = 616. (7) = 816. 0.1 0.2 0.3 0.4 f/fs 0.5
Fig.15 Transfer function of peaking low band-pass with variation of ( = 0; = 0).
handbook, halfpage
output
-cor_thr cor_thr input
MHC193
Fig.16 Peaking coring function.
2002 May 28
40
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
13 APPLICATION INFORMATION
SAA4979H
The SAA4979H supports different scan-rate upconversion concepts. The simple one is illustrated in Fig.17. In this application no further components are needed for a 100 Hz conversion based on a field repetition algorithm (AABB mode). The system can be upgraded by a vector based motion estimation and compensation function. In this case the SAA4992H together with two field memories (SAA4955) are needed (see Figs 18 and 19 respectively). In addition the SAA4979H supports field based and frame based picture-in-picture applications. To realize the full performance frame based PIP function a second video decoder (SAA7118) and two additional field memories are required (see Fig.20).
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41
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
handbook, full pagewidth
+ 3.3 V 10 F + 3.3 V n.c. RST RSTW2 18 6 106, 118 113 to 116, 119 to 127 5, 15, 27 1, 17, 29 64, 53, 61, 63, 89, 82, 105 104 99, 94, 117 109 8.2 k + 3.3 V + 3.3 V + 3.3 V
8
19 to 26 83 IE n.c.
n.c. n.c. n.c.
RSTR2 RE2 OIE2 LLC2
2 3 4 28 112 111
110 107
SNRST SNCL SNDA 16
n.c. n.c. n.c.
SCL SDA
108
SAA4979H
CVBS MAIN YC MAIN YUVMAIN RGB MAIN FSWMAIN 24.576 MHz + 3.3 V + 3.3 V + 3.3 V n.c. SAA7118 VIDEO DECODER LLC1 YCRCB 7 to 14 ITU 656 8 16
85 to 88, 90 to 93, 95 to 98, 100 to 103 84
n.c. REO
81 65 to 80
REI 16 n.c. CLK32 n.c.
BCE TCK TDI TMS TRST TDO
128 30 31 32 33 42 43 44 46 48 45, 49, 50, 56 54 47, 52, 57 58 + 3.3 V 12 MHz 34 to 41, 51, 60 62
n.c.
55
59
LOW PASS
+ 3.3 V
LOW PASS
12 pF
18 pF
LOW PASS HD VD
MHC194
Fig.17 Application diagram 1.
2002 May 28
42
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
handbook, full pagewidth
+ 3.3 V 10 F + 3.3 V n.c. RST RSTW2 18 6 106, 118 113 to 116, 119 to 127 5, 15, 27 1, 17, 29 64, 53, 61, 63, 89, 82, 105 104 99, 94, 117 109 8.2 k + 3.3 V + 3.3 V + 3.3 V
CVBS PIP YC PIP YUVPIP RGB PIP FSWPIP PIP MODULE
YCRCB 19 to 26 ITU 656 8 RSTR2 RE2 OIE2 LLC1 2 3 4 28
83
A
110 107
B C D
SCL SDA
112 111
108
SAA4979H
SAA7118 VIDEO DECODER LLC1 YCRCB 7 to 14 ITU 656 24.576 MHz + 3.3 V + 3.3 V + 3.3 V 8 16
85 to 88, 90 to 93, 95 to 98, 100 to 103 84 REI
E F
81 65 to 80
G H
BCE TCK TDI TMS TRST n.c. TDO
128 30 31 32 33 42 43 44 46 48 45, 49, 50, 56 54 47, 52, 57 58 12 MHz
16 62 I
34 to 41, 51, 60
n.c.
55
59
LOW PASS
+ 3.3 V
+ 3.3 V
LOW PASS
12 pF
18 pF
LOW PASS HD VD
MHC195
J
Fig.18 Application diagram 2 (continued in Fig.19).
2002 May 28
43
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
handbook, full pagewidth
+ 3.3 V
+ 3.3 V
19, 22 3 to 14 + 3.3 V + 3.3 V + 3.3 V + 3.3 V 12 2 to 13 14 146 147 to 152, 154 to 159 12 27 to 38 24
20, 21 23 25 26 + 3.3 V CLK32 VD
20
19
A
16, 21, 69, 90, 102, 113, 141, 153, 160
18, 22, 56, 57, 101, 103, 138, 142
SAA4955TJ 17 15 16 18 CLK32 VD IE
1, 2, 39, 40 SNRST SNCL SNDA
B C D
25 27 26
136, 139, 140, 144
n.c.
31 16 E F REO 37 to 52 60
TRST TMS TDI TDO TCK + 3.3 V + 3.3 V n.c. + 3.3 V
SAA4992H
32 33 34 35
G H I CLK32
53 61 to 68, 70 to 77 79 24, 82 to 89, 29, 91 to 98 30 12 12 n.c. 27 to 38 1, 2, 39, 40 + 3.3 V 1, 15, 28, 36, 54, 59, 17, 23, 78, 81, 55, 58, 99, 105, 80, 100, 120, 121, 104, 137, 135, 145 143 + 3.3 V
12 122 to 133 107 to 112, 134 114 to 119 106
19, 22 3 to 14 24
20, 21 23 25 26 + 3.3 V CLK32 VD
SAA4955TJ 17 15 16 18 CLK32 VD IE
J
MHC196
Fig.19 Application diagram 3 (continued from Fig.18).
2002 May 28
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ndbook, full pagewidth
2002 May 28 2002 May 28
SCL SDA + 3.3 V CVBS PIP YC PIP YUVPIP RGB PIP FSWPIP SAA7118 VIDEO DECODER 1 10 24.576 MHz SWCK2 11 20 8 74F574 2 to 9 12 to 19
Philips Semiconductors
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
+ 3.3 V
+ 3.3 V
19, 22 3 to 6 8
20, 21 35 to 38 n.c.
7 to 14 27 to 34 SAA4955TJ SWCK2 RSTW2 WE2 IE2 15 16 17 18 1, 2, 39, 40 26 25 24 23
RSTW2 YCRCB ITU 656
8 + 3.3 V + 3.3 V
45 45
19, 22 3 to 6 8
20, 21 35 to 38 n.c.
7 to 14 27 to 34 SAA4955TJ SWCK2 RSTW2 WE2 15 16 17 18 1, 2, 39, 40
MHC197
26 25 24 23
LLC1 RSTR2 RE2 OIE2
Product specification
SAA4979H
Fig.20 PIP module.
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4979H
handbook, halfpage
8.2 pF 2.7 H Vout 15 pF 68 pF
MHC198
240 Vin
Fig.21 Low-pass filter.
handbook, full pagewidth
+8 V 5.1 k
+8 V 240 100
+8 V
10 F Vin BC846 200 2.7 k 200
BC856
4.7 pF 4.7 H Vout 39 pF 39 pF 240
MHC199
240
Fig.22 Low-pass filter with termination.
2002 May 28
46
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
14 PACKAGE OUTLINE QFP128: plastic quad flat package; 128 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height
SAA4979H
SOT320-2
c
y
X
A 96 97 65 64 ZE
e E HE A A2 A1 (A 3) Lp L detail X 33 1 bp D HD wM ZD B vM B 32 vM A
wM bp pin 1 index 128
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT320-2 REFERENCES IEC 134E13 JEDEC MS-022 EIAJ EUROPEAN PROJECTION A max. 4.07 A1 0.50 0.25 A2 3.70 3.15 A3 0.25 bp 0.45 0.30 c 0.23 0.13 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.8 HD HE L 1.6 Lp 1.03 0.73 v 0.3 w 0.2 y 0.1 Z D (1) Z E(1) 1.8 1.4 1.8 1.4 7 0o
o
31.45 31.45 30.95 30.95
ISSUE DATE 99-12-27 00-01-19
2002 May 28
47
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
15 SOLDERING 15.1 Introduction to soldering surface mount packages
SAA4979H
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
SAA4979H
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 May 28
49
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
16 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
SAA4979H
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 17 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 May 28
50
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality dynamic noise reduction and expansion port
19 PURCHASE OF PHILIPS I2C COMPONENTS
SAA4979H
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2002 May 28
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/01/pp52
Date of release: 2002
May 28
Document order number:
9397 750 09561

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